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ds96lv00800 p r e l i m i n a r y 1 1 p reliminary p roduct s pecification z86l88/81/86/87/89/73 1 ir/l ow -v oltage m icrocontroller features n low power consumption - 40 mw (typical) n three standby modes stop halt low voltage n special architecture to automate both generation and reception of complex pulses or signals: one programmable 8-bit counter/timer with two capture registers one programmable 16-bit counter/timer with one 16-bit capture register programmable input glitch filter for pulse reception n five priority interrupts three external two assigned to counter/timers n low voltage detection and standby mode n programmable watch-dog/power-on reset circuits n two independent comparators with programmable interrupt polarity n on-chip oscillator that accepts a crystal, ceramic resonator, lc, rc (mask option), or external clock drive n mask selectable 200 kohms pull-ups on ports 0, 2, 3 all eight port 2 bits at one time or not pull-ups automatically disabled upon selecting individual pins as outputs. n maskable mouse/trackball interface on p00 through p03. n 32 khz oscillator mask option general description the z86lxx family of ir (infrared) ccp (consumer con- troller processor) controllers are rom/romless-based members of the z8 single-chip microcontroller family with 256 bytes of internal ram. the differentiating factor be- tween these devices is the availability of rom, and pack- age options. for the 40 and 44-pin devices the use of ex- ternal memory enables these z8 microcontrollers to be used where code flexibility is required. zilog? cmos mi- crocontrollers offers fast executing, efficient use of memo- ry, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and in- ternal key-scan pull-up resistors. the z86lxx product line offers easy hardware/software system expansion cost-ef- fective and low power consumption. the z86lxx architecture is based on zilog's 8-bit micro- controller core with an expanded register file to allow ac- cess to register mapped peripherals, i/o circuits, and pow- erful counter/timer circuitry. the ccp offers a flexible i/o scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many device rom (kb) ram* (bytes) i/o lines voltage range z86l88 16 237 23 2.0v to 3.9v z86l81 24 237 23 2.0v to 3.9v z86l86 32 237 23 2.0v to 3.9v z86l87 16 236 31 2.0v to 3.9v z86l89 24 236 31 2.0v to 3.9v z86l73 32 236 31 2.0v to 3.9v note: *general-purpose
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 2 p r e l i m i n a r y ds96lv00800 general description (continued) consumer, automotive, computer peripheral, and battery operated hand-held applications. there are four basic address spaces available to support a wide range of configurations: program memory, regis- ter file, expanded register file, and external memory. the register file is composed of 256 bytes of ram. it in- cludes four i/o port registers, 16 control and status regis- ters and the rest are general purpose registers. the ex- panded register file consists of two additional register groups (f and d). external memory is not available on 28- pin versions. to unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the z86lxx family offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (figure 1). also includ- ed are a large number of user-selectable modes, and two on-board comparators to process analog signals with sep- arate reference voltages (figure 2). notes: all signals with a preceding front slash, "/", are ac- tive low, e.g., b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions be- low: connection circuit device power v cc v dd ground gnd v ss figure 1. counter/timers diagram hi16 lo16 16-bit t16 tc16h tc16l hi8 lo8 and/or logic clock divider glitch filter edge detect circuit 8-bit t8 tc8h tc8l 8 8 16 8 input sclk 1 2 48 timer 16 timer 8/16 timer 8 8 8 8 8 8
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 3 1 figure 2. functional block diagram port 0 p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 p21 p22 p23 p24 p25 p26 p27 pref1 p31 p32 p33 /as /ds r/w /reset port 3 port 1 port 2 register file 256 x 8-bit rom 24k/32k x 8 z8 core register bus internal address bus internal data bus expanded register file expanded register bus counter/timer 8 8-bit counter/timer 16 16-bit machine timing & instruction control power xtal vdd vss p34 p35 p36 p37 4 4 8 i/o bit programmable r//rl (44-pin)
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 4 p r e l i m i n a r y ds96lv00800 pin description figure 3. 28-pin dip pin assignments figure 4. 28-pin soic pin assignments p25 p26 p27 p04 p05 p06 p07 vdd xtal2 xtal1 p31 p32 p33 p34 p24 p23 p22 p21 p20 p03 vss p02 p01 p00 pref1 p36 p37 p35 28 z86l88/86/81 dip 1 14 15 p25 p26 p27 p04 p05 p06 p07 vdd xtal2 xtal1 p31 p32 p33 p34 p24 p23 p22 p21 p20 p03 vss p02 p01 p00 pref1 p36 p37 p35 28 z86l88/86/81 soic 1 14 15
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 5 1 figure 5. 40-pin dip pin assignments r//w p25 p26 p27 p04 p05 p06 p14 p15 p07 vdd p16 p17 xtal2 xtal1 p31 p32 p33 p34 /as /ds p24 p23 p22 p21 p20 p03 p13 p12 vss p02 p11 p10 p01 p00 pref1 p36 p37 p35 /reset 40 z86l73/89/87 dip 1 20 21 figure 6. 44-pin plcc pin assignments z86l73/89/73 plcc 7 17 p21 p22 p23 p24 /ds r//rl r//w p25 p26 p27 p04 pref1 p36 p37 p35 /reset vss /as p34 p33 p32 p31 p05 p06 p14 p15 p07 vdd vdd p16 p17 xtal2 xtal1 p20 p03 p13 p12 vss vss p02 p11 p10 p01 p00 1 28 18 40 39 29 6
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 6 p r e l i m i n a r y ds96lv00800 pin description (continued) figure 7. 44-pin qfp pin assignments 34 44 p21 p22 p23 p24 /ds r//rl r//w p25 p26 p27 p04 pref1 p36 p37 p35 /reset vss /as p34 p33 p32 p31 p05 p06 p14 p15 p07 vdd vdd p16 p17 xtal2 xtal1 p20 p03 p13 p12 vss vss p02 p11 p10 p01 p00 1 23 33 z86l73/89/87 qfp 11 22 12
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 7 1 table 1. pin identi?ation 40-pin dip # 44-pin plcc # 44-pin qfp # symbol direction description 26 40 23 p00 input/output port 0 is nibble programmable. 27 41 24 p01 input/output port 0 can be con?ured as 30 44 27 p02 input/output a15-a8 external program 34 5 32 p03 input/output rom address bus. 5 17 44 p04 input/output port 0 can be con?ured as a 6 18 1 p05 input/output mouse/trackball input. 7 19 2 p06 input/output 10 22 5 p07 input/output 28 42 25 p10 input/output port 1 is byte programmable. 29 43 26 p11 input/output port 1 can be con?ured as 32 3 30 p12 input/output multiplexed a7-a0/d7-d0 33 4 31 p13 input/output external program rom 8 20 3 p14 input/output address/data bus. 9 21 4 p15 input/output 12 25 8 p16 input/output 13 26 9 p17 input/output 35 6 33 p20 input/output port 2 pins are individually 36 7 34 p21 input/output con?urable as input or output. 37 8 35 p22 input/output 38 9 36 p23 input/output 39 10 37 p24 input/output 2 14 41 p25 input/output 3 15 42 p26 input/output 4 16 43 p27 input/output 16 29 12 p31 input irq2/modulator input 17 30 13 p32 input irq0 18 31 14 p33 input irq1 19 32 15 p34 output t8 output 22 36 19 p35 output t16 output 24 38 21 p36 output t8/t16 output 23 37 20 p37 output 20 33 16 /as output address strobe 40 11 38 /ds output data strobe 1 13 40 r//w output read/write 21 35 18 /reset input reset 15 28 11 xtal1 input crystal, oscillator clock 14 27 10 xtal2 output crystal, oscillator clock 11 23,24 6,7 v dd power supply 31 1,2, 34 17,28,29 v ss ground 25 39 22 pref1 input comparator 1 reference 12 39 r//rl input rom/romless
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 8 p r e l i m i n a r y ds96lv00800 pin description (continued) table 2. pin identi?ation 28-pin dip & soic symbol direction description 19 p00 input/output port 0 is nibble programmable 20 p01 input/output port 0 can be con?ured as 21 p02 input/output a15-a8 external program 23 p03 input/output rom address bus. 4 p04 input/output 5 p05 input/output port 0 can be con?ured as a mouse/trackball input. 6 p06 input/output 7 p07 input/output 24 p20 input/output port 2 pins are individually 25 p21 input/output con?urable as input or output. 26 p22 input/output 27 p23 input/output 28 p24 input/output 1 p25 input/output 2 p26 input/output 3 p27 input/output 18 pref1 input analog ref input 11 p31 input irq2/modulator input 12 p32 input irq0 13 p33 input irq1 14 p34 output t8 output 15 p35 output t16 output 17 p36 output t8/t16 output 16 p37 output 10 xtal1 input crystal, oscillator clock 9 xtal2 output crystal, oscillator clock 8v dd power supply 22 v ss ground
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 9 1 absolute maximum ratings stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; operation of the device at any condition above those indicated in the operational sec- tions of these specifications is not implied. exposure to ab- solute maximum rating conditions for an extended period may affect device reliability. standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (figure 8). capacitance t a = 25 c, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to gnd. symbol description min max units v cc supply voltage (*) ?.3 +7.0 v t stg storage temp. ?5 +150 c t a oper. ambient temp. ?c notes: : * voltage on all pins with respect to gnd. ? see ordering information. figure 8. test load diagram from output under test 150 pf i parameter max input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 10 p r e l i m i n a r y ds96lv00800 dc characteristics preliminary t a = 0 c to +70 c typ @ sym parameter v cc min max 25 c units conditions notes max input voltage 2.0v 3.9v 7 7 v v i in <250 m a i in <250 m a v ch clock input high voltage 2.0v 3.9v 0.8 v cc 0.8 v cc v cc + 0.3 v cc + 0.3 v v driven by external clock generator driven by external clock generator v cl clock input low voltage 2.0v 3.9v v ss ?0.3 v ss ?0.3 0.2 v cc 0.2 v cc v v driven by external clock generator driven by external clock generator v ih input high voltage 2.0v 3.9v 0.7 v cc 0.7 v cc v cc + 0.3 v cc + 0.3 0.5v cc 0.5v cc v v v il input low voltage 2.0v 3.9v v ss ?0.3 v ss ?0.3 0.2 v cc 0.2 v cc 0.5v cc 0.5v cc v v v oh1 output high voltage 2.0v 3.9v v cc ?0.4 v cc ?0.4 1.7 3.7 v v i oh = ?.5 ma i oh = ?.5 ma v oh2 output high voltage (p36, p37,p00, p01) 2.0v 3.9v v cc - 0.8 v cc - 0.8 v v i oh = ? ma i oh = ? ma v ol1 output low voltage 2.0v 3.9v 0.4 0.4 0.1 0.2 v v i ol = 1.0 ma i ol = 4.0 ma v ol2* output low voltage 2.0v 3.9v 0.8 0.8 0.5 0.3 v v i ol = 5.0 ma i ol = 7.0 ma v ol2 output low voltage(p36, p37,p00,p01) 2.0v 3.9v 0.8 0.8 0.3 0.2 v v i ol = 10 ma i ol = 10 ma v rh reset input high voltage 2.0v 3.9v 0.8 v cc 0.8 v cc v cc v cc 1.5 2.0 v v v rl reset input low voltage 2.0v 3.9v v ss ?0.3 v ss ?0.3 0.2 v cc 0.2 v cc 0.5 0.9 v v v offset comparator input offset voltage 2.0v 3.9v 25 25 10 10 mv mv i il input leakage 2.0v 3.9v -1 -1 1 1 < 1 < 1 m a m a v in = o v , v cc v in = o v , v cc i ol output leakage 2.0v 3.9v ? ? 1 1 < 1 < 1 m a m a v in = o v , v cc v in = o v , v cc i ir reset input pull- up current 2.0v 3.9v ?30 ?00 -90 ?20 m a m a v in = o v v in = o v i cc supply current 2.0v 3.9v 10 15 4 10 ma ma @ 8.0 mhz @ 8.0 mhz 1,2 1,2 2.0v 3.9v 250 850 100 500 m a m a @ 32 khz @ 32 khz 1,2,7 1,2,7
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 11 1 t a = 0 c to +70 c typ @ sym parameter v cc min max 25 c units conditions notes i cc1 standby current (wdt off) 2.0v 3.9v 3 5 1 4 ma ma halt mode v in = o v , v cc @ 8.0 mhz halt mode v in = o v , v cc @ 8.0 mhz 1,2 1,2 2.0v 3.9v 2 4 0.8 2.5 ma ma clock divide-by- 16 @ 8.0 mhz clock divide-by- 16 @ 8.0 mhz 1,2 1,2 i cc2 standby current 2.0v 3.9v 8 10 2 3 m a m a stop mode v in = o v , v cc wdt is not running stop mode v in = o v , v cc wdt is not running 3,5 3,5 2.0v 3.9v 500 800 310 600 m a m a stop mode v in = o v , v cc wdt is running 3,5 t por power-on reset 2.0v 3.9v 12 5 75 20 18 7 ms ms vram static ram data retention voltage vram 0.8 0.5 v 6 v lv (vbo) v cc low voltage protection 2.15 1.7 v 8 mhz max ext. clk freq. 4 notes: i cc1 crystal/resonator external clock drive typ 3.0 ma 0.3 ma max 5 5 unit ma ma frequency 8.0 mhz 8.0 mhz 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf 3. same as note [4] except inputs at v cc . 4. the v lv increases as the temperature decreases. 5. oscillator stopped. 6. oscillator stops when vcc falls below vlv limit 7. 32 khz clock driver input. * all outputs excluding p00, p01, p36, and p37.
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 12 p r e l i m i n a r y ds96lv00800 ac characteristics external i/o or memory read and write timing diagram figure 9. external i/o or memory read/write timing r//w 9 12 18 3 16 13 4 5 8 11 6 17 10 15 14 2 1 port 0, /dm port 1 /as /ds (read) port 1 /ds (write) a7 - a0 d7 - d0 in d7 - d0 out a7 - a0 19 20 7
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 13 1 ac characteristics preliminary external i/o or memory read and write timing table t a = 0 c to +70 c 8.0mhz no symbol parameter v cc min max units notes 1 tda(as) address valid to /as rising delay 2.0v 3.9v 55 55 ns ns 2 2 tdas(a) /as rising to address float delay 2.0v 3.9v 70 70 ns ns 2 2 3 tdas(dr) /as rising to read data required valid 2.0v 3.9v 400 400 ns ns 1,2 4 twas /as low width 2.0v 3.9v 80 80 ns ns 2 5 td address float to /ds falling 2.0v 3.9v 0 0 ns ns 6 twdsr /ds (read) low width 2.0v 3.9v 300 300 ns ns 1,2 7 twdsw /ds (write) low width 2.0v 3.9v 165 165 ns ns 1,2 8 tddsr(dr) /ds falling to read data required valid 2.0v 3.9v 260 260 ns ns 1,2 9 thdr(ds) read data to /ds rising hold time 2.0v 3.9v 0 0 ns ns 2 10 tdds(a) /ds rising to address active delay 2.0v 3.9v 85 95 ns ns 2 11 tdds(as) /ds rising to /as falling delay 2.0v 3.9v 60 70 ns ns 2 12 tdr/w(as) r//w valid to /as rising delay 2.0v 3.9v 70 70 ns ns 2 13 tdds(r/w) /ds rising to r//w not valid 2.0v 3.9v 70 70 ns ns 2 14 tddw(dsw) write data valid to /ds falling (write) delay 2.0v 3.9v 80 80 ns ns 2 15 tdds(dw) /ds rising to write data not valid delay 2.0v 3.9v 70 80 ns ns 2 16 tda(dr) address valid to read data required valid 2.0v 3.9v 475 475 ns ns 1,2 17 tdas(ds) /as rising to /ds falling delay 2.0v 3.9v 100 100 ns ns 2 18 tddm(as) /dm valid to /as falling delay 2.0v 3.9v 55 55 ns ns 2 19 tdds(dm) /ds rise to /dm valid delay 2.0v 3.9v 70 70 ns ns 20 thds(a) /ds rise to address valid hold time 2.0v 3.9v 70 70 ns notes: 1. when using extended memory timing add 2 tpc. 2. timing numbers given are for minimum tpc. standard test load all timing references use 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0.
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 14 p r e l i m i n a r y ds96lv00800 ac characteristics additional timing diagram figure 10. additional timing clock 1 3 4 8 2 2 3 t irq in n 6 5 7 7 clock setup 10 9 stop mode recovery source 11
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 15 1 ac characteristics preliminary additional timing table t a = 0 c to +70 c 8.0mhz no sym parameter v cc min max units notes 1 tpc input clock period 2.0v 3.9v 121 121 dc dc ns ns 1 1 2 trc,tfc clock input rise and fall times 2.0v 3.9v 25 25 ns ns 1 1 3 twc input clock width 2.0v 3.9v 37 37 ns ns 1 1 4 twtinl timer input low width 2.0v 3.9v 100 70 ns ns 1 1 5 twtinh timer input high width 2.0v 3.9v 3tpc 3tpc 1 1 6 tptin timer input period 2.0v 3.9v 8tpc 8tpc 1 1 7 trtin,tftin timer input rise and fall timers 2.0v 3.9v 100 100 ns ns 1 1 8a twil interrupt request low time 2.0v 3.9v 100 70 ns ns 1,2 1,2 8b twil interrupt request low time 2.0v 3.9v 5tpc 5tpc 1,3 1,3 9 twih interrupt request input high time 2.0v 3.9v 5tpc 5tpc 1,2 1,2 10 twsm stop-mode recovery width spec 2.0v 3.9v 2.0v 3.9v 12 12 5 tpc 5 tpc ns ns ns ns 7 7 6 6 11 tost oscillator start-up time 2.0v 3.9v 5tpc 5tpc 4 4 12 twdt watch-dog timer delay time (5 ms) (10 ms) (20 ms) (80 ms) 2.0v 3.9v 2.0v 3.9v 2.0v 3.9v 2.0v 3.9v 12 5 25 10 50 20 225 80 75 20 150 40 300 80 1200 320 ms ms ms ms ms ms ms ms notes: 1. timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2. interrupt request through port 3 (p33-p31). 3. interrupt request through port 3 (p30). 4. smr ?d5 = 0
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 16 p r e l i m i n a r y ds96lv00800 ac characteristics handshake timing diagrams figure 11. port input handshake timing data in 1 3 4 5 6 /dav (input) rdy (output) next data in valid delayed rdy delayed dav data in valid 2 figure 12. port output handshake timing data out /dav (output) rdy (input) next data out valid delayed rdy delayed dav data out valid 7 8 9 10 11
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 17 1 ac characteristics preliminary handshake timing table t a = 0 c to +70 c data no sym parameter v cc min max direction 1 tsdi(dav) data in setup time 2.0v 3.9v 0 0 in in 2 thdi(dav) data in hold time 2.0v 3.9v 0 0 in in 3 twdav data available width 2.0v 3.9v 155 110 in in 4 tddavi(rdy) dav falling to rdy falling delay 2.0v 3.9v 160 115 in in 5 tddavid(rdy) dav rising to rdy falling delay 2.0v 3.9v 120 80 in in 6 tdrdyo(dav) rdy rising to dav falling delay 2.0v 3.9v 0 0 in in 7 tddo(dav) data out to dav falling delay 2.0v 3.9v 63 63 out out 8 tddav0(rdy) dav falling to rdy falling delay 2.0v 3.9v 0 0 out out 9 tdrdy0(dav) rdy falling to dav rising delay 2.0v 3.9v 160 115 out out 10 twrdy rdy width 2.0v 3.9v 110 80 out out 11 tdrdy0d(dav) rdy rising to dav falling delay 2.0v 3.9v 110 80 out out
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 18 p r e l i m i n a r y ds96lv00800 pin functions /ds (output, active low). data strobe is activated once for each external memory transfer. for a read operation, data must be available prior to the trailing edge of /ds. for write operations, the falling edge of /ds indicates that output data is valid. /as (output, active low). address strobe is pulsed once at the beginning of each machine cycle. address output is through port 0/port 1 for all external programs. memory address transfers are valid at the trailing edge of /as. un- der program control, /as is placed in the high-impedance state along with ports 0 and 1, data strobe, and read/write. xtal1 crystal 1 (time-based input). this pin connects a parallel-resonant crystal, ceramic resonator, lc, or rc network or an external single-phase clock to the on-chip oscillator input. xtal2 crystal 2 (time-based output). this pin connects a parallel-resonant, crystal, ceramic resonant, lc, or rc network to the on-chip oscillator output. r//w read/write (output, write low). the r//w signal is low when the ccp is writing to the external program or data memory. r//rl (input). this pin, when connected to gnd, disables the internal rom and forces the device to function as a romless z8. (note that, when left unconnected or pulled high to v cc , the part functions normally as a z8 rom ver- sion.) port 0 (p07-p00). port 0 is an 8-bit, bidirectional, cmos compatible port. these eight i/o lines are configured un- der software control as a nibble i/o port, or as an address port for interfacing external memory. the output drivers are push-pull. port 0 can be placed under handshake con- trol. in this configuration, port 3, lines p32 and p35 are used as the handshake control /dav0 and rdy0. hand- shake signal function is dictated by the i/o direction of the port 0 upper nibble p07-p04. the lower nibble must have the same direction as the upper nibble. for external memory references, port 0 can provide ad- dress bits a11-a8 (lower nibble) or a15-a8 (lower and up- per nibble) depending on the required address space. if the address range requires 12 bits or less, the upper nibble of port 0 can be programmed independently as i/o while the lower nibble is used for addressing. if one or both nib- bles are needed for i/o operation, they must be configured by writing to the port 0 mode register. after a hardware re- set, port 0 is configured as an input port. port 0 is set in the high-impedance mode (if selected as an address output) along with port 1 and the control signals /as, /ds, and r//w through p3m bits d4 and d3(figure 13). a rom mask option is available to program 0.4 v dd cmos trip inputs on p00-p03. this allows direct interface to mouse/trackball ir sensors. an optional 200 kohms pull-up is available as a mask op- tion on all port 0 bits with nibble select. note: internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode.
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 19 1 figure 13. port 0 con?uration z86lxx mcu 4 4 port 0 (i/o or a15 - a8) optional handshake controls /dav0 and rdy0 (p32 and p35) oen out in pa d 200 k w * mask selectable refer to the z86c17 specification for application information in utilizing these inputs in a mouse or trackball application. mask option in 0.4 vdd trip point buffer
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 20 p r e l i m i n a r y ds96lv00800 pin functions (continued) port 1 (p17-p10). port 1 is a multiplexed address (a7-a0) and data (d7-d0), cmos compatible port. port 1 is dedi- cated to the zilog zbus -compatible memory interface. the operations of port 1 are supported by the address strobe (/as) and data strobe (/ds) lines, and by the read/write (r//w) and data memory (/dm) control lines. data memory read/write operations are done through this port (figure 14). if more than 256 external locations are re- quired, port 0 outputs the additional lines. port 1 can be placed in the high-impedance state along with port 0, /as, /ds, and r//w, allowing the z86lxx to share common resources in multiprocessor and dma ap- plications. port1 can also be configured for standard port output mode.. figure 14. port 1 con?uration port 1 (i/o or ad7 - ad0) optional handshake controls /dav1 and rdy1 (p33 and p34) z86lxx mcu 8 oen out in pa d auto latch r ? 500 k w
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 21 1 port 2 (p27-p20). port 2 is an 8-bit, bidirectional, cmos compatible i/o port. these eight i/o lines can be indepen- dently configured under software control as inputs or out- puts. port 2 is always available for i/o operation. a mask option is available to connect eight 200 kohms ( 50%) pull-up resistors on this port. bits programmed as outputs are globally programmed as either push-pull or open- drain. port 2 may be placed under handshake control. in this configuration, port 3 lines, p31 and p36 are used as the handshake controls lines /dav2 and rdy2. the hand- shake signal assignment for port 3, lines p31 and p36 is dictated by the direction (input or output) assigned to bit 7, port 2 (figure 15). the ccp por resets with the eight bits of port 2 configured as inputs with open-drain outputs. port 2 also has an 8-bit input or and an and gate which can be used to wake up the part (figure 41). p20 can be programmed to access the edge selection circuitry (figure 24). figure 15. port 2 con?uration open-drain oen out in pa d port 2 (i/o) optional handshake controls /dav2 and rdy2 (p31 and p36) z86lxx mcu vcc 200 k w mask option
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 22 p r e l i m i n a r y ds96lv00800 pin functions (continued) port 3 (p37-p31). port 3 is a 7-bit, cmos compatible three fixed input and four fixed output port. port 3 consists of three fixed input (p33-p31) and four fixed output (p37- p34), and can be configured under software control for in- put/output, interrupt, port handshake, data memory func- tions and output from the counter/timers. p31, p32, and p33 are standard cmos inputs; outputs are push-pull. two on-board comparators process analog signals on p31 and p32 with reference to the voltage on pref1 and p33. the analog function is enabled by programming the port 3 mode register (bit 1). p31 and p32 are programmable as rising, falling, or both edge triggered interrupts (irq regis- ter bits 6 and 7). pref1 and p33 are the comparator refer- ence voltage inputs. access to the counter timer edge de- tection circuit is through p31 or p20 (see ctr1 description). other edge detect and irq modes are de- scribed in tables (3-6). handshake lines ports 0, 1, and 2 are available on p31 through p36. port 3 provides the following control functions: handshake for ports 0, 1, and 2 (/dav and rdy); three external inter- rupt request signals (irq2-irq0); data memory select (/dm) (table 3). port 3 also provides output for each of the counter/timers and the and/or logic. control is performed by program- ming bits d5-d4 of ctr1, bit 0 of ctr0 and bit 0 of ctr2. comparator inputs . in analog mode, port 3 (p31 and p32) have a comparator front end. the comparator refer- ence is supplied to p33 and pref1. in this mode, the p33 internal data latch and its corresponding irq1 is diverted to the smr sources (excluding p31,p32, and p33) as shown in figure 41. in digital mode, p33 is used as d3 of the port 3 input register which then generates irq1 as shown in figure 17. when p31 is used for counter timer input (demodulation mode), input is always taken from the p31 digital input buffer whether or not analog mode is enabled). notes: comparators are powered down by entering stop mode. for p31-p33 to be used in a stop-mode recovery source, these inputs must be placed into digital mode. comparator outputs . these may be programmed to be outputted on p34 and p37 through the pcon register (fig- ures 16,38). /reset (input, active low). initializes the mcu. reset is accomplished either through power-on, watch-dog tim- er, stop-mode recovery, low voltage detection, or exter- nal reset. during power-on reset and watch-dog timer reset, the internally generated reset drives the reset pin low for the por time. any devices driving the external re- set line should be open-drain in order to avoid damage from a possible conflict during reset conditions. pull-up is provided internally. table 3. pin assignments pin i/o c/t comp. int. p0 hs p1 hs p2 hs ext pref1 in rf1 p31 in in an1 irq2 d/r p32 in an2 irq0 d/r p33 in rf2 irq1 d/r p34 out t8 ao1 r/d dm p35 out t16 r/d p36 out t8/16 r/d p37 out ao2 p20 i/o in notes: d = /dav r = rdy hs = handshake signals
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 23 1 figure 16. port 3 con?uration p34 out p37 out p32 + - p33 (pref2) 0 = p34, p37 standard output 1 = p34, p37 comparator output pcon d0 p31 + - pref1 p37 pa d p34 pa d * t8 p34 out 0 normal control 1 8-bit timer output active ctr0 d0 counter/timer reset condition. * comp1 comp2
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 24 p r e l i m i n a r y ds96lv00800 pin functions (continued) after the por time, /reset is a schmitt-triggered input. to avoid asynchronous and noisy reset problems, the z86lxx is equipped with a reset filter of four external clocks (4tpc). if the external reset signal is less than 4tpc in duration, no reset occurs. on the fifth clock after the re- set is detected, an internal rst signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. during the reset cycle, /ds is held active low while /as cy- cles at a rate of tpc/2. program execution begins at loca- tion 000ch, 5-10 tpc cycles after the rst is released. for power-on reset, the typical reset output time is 5 ms. the z86lxx does not reset wdtmr, smr, p2m, or p3m reg- isters on a stop-mode recovery operation. the output states of port3 and port2 are also un-affected by a stop- mode recovery. figure 17. port 3 con?uration port 3 (i/o or handshake) z86l7x mcu pref1 p31 p32 p33 p34 p35 p36 p37 note: p31, 32, 33 have a 200 k w mask option 200 k w mask option d1 r247 = p3m p31 (an1) p32 (an2) p33 (ref2) from stop-mode recovery source of smr 1 = analog 0 = digital irq2, p31 data latch irq0, p32 data latch irq1, p33 data latch dig. an. - + - + pref comp1 comp2
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 25 1 figure 18. port 3 counter timer output con?uration vdd out 34 t8_out ctr0, d0 pad out 35 t16_out ctr2, d0 out 36 t8/16_out ctr1, d6 mux mux mux p34 vdd pad p35 vdd pad p36
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 26 p r e l i m i n a r y ds96lv00800 functional description the z86lxx family of ir ccp incorporates special func- tions to enhance the z8's functionality in consumer and battery operated applications. program memory . the z86lxx family addresses 16/24/32 kbytes of internal program memory. the first twelve bytes are reserved for interrupt vectors. these lo- cations contain the five 16-bit vectors which correspond to the five available interrupts. in all cases, at addresses 32k and greater, external program memory fetches will be ex- ecuted (provided proper a/d port mode register settings). refer to external memory timing specifications. in rom- less mode, program memory fetches begin at address 000ch and data memory fetches begin at address 0000h. ram. the z86lxx devices all have 256 bytes of ram which make up the register file. external memory (/dm). the z86lxx addresses up to 32 kbytes of external memory beginning at address 32768 (figure 20). external data memory is included with, or sep- arated from, the external program memory space. /dm, an optional i/o function that is programmed to appear on p34, is used to distinguish between data and program memory space. the state of the /dm signal is controlled by the type of instruction being executed. an ldc opcode references program (/dm inactive) memory, and an lde instruc- tion references data (/dm active low) memory. figure 19. program memory map(32k rom) 11 10 9 8 7 6 5 4 3 2 1 0 external rom location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) reserved irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 reserved on-chip rom 32768 reset start address 12 figure 20. external memory map 65535 0 external data memory not addressable 32,768
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 27 1 expanded register file. the register file has been ex- panded to allow for additional system control registers, and for mapping of additional peripheral devices into the register address area. the z8 register address space r0 through r15 has been implemented as 16 banks of 16 reg- isters per bank. these register groups are known as the erf (expanded register file). bits 7-4 of register rp se- lect the working register group. bits 3-0 of register rp se- lect the expanded register file bank. note that expanded register bank is also referred to as expanded register group (figure 21). the upper nibble of the register pointer (figure 23) selects which working register group of 16 bytes in the register file, out of the possible 256, will be accessed. the lower nibble selects the expanded register file bank and, in the case of the z86lxx family, banks 0, f, and d are implemented. a 0h in the lower nibble will allow the normal register file (bank 0) to be addressed, but any other value from 1h to fh will exchange the lower 16 registers to an expanded register bank. for example: z86l73: (see figure 21) r253 rp = 00h r0 = port 0 r1 = port 1 r2 = port 2 r3 = port 3 but if: r253 rp = 0dh r0 = ctrl0 r1 = ctrl1 r2 = ctrl2 r3 = reserved the counter/timers are mapped into erf group d. access is easily done using the following example: ld rp, #0dh select erf d for access to bank d ( work- ing register group 0) ld r0,#xx load ctrl0 ld 1, #xx load ctrl1 ld r1, 2 ctrl2 ? ctrl1 ld rp, #7dh select expanded register bank d and working register group 7 of bank 0 for access . ld 71h, 2 ctrl2 ? register 71h ld r1, 2 ctrl2 ? register 71h
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 28 p r e l i m i n a r y ds96lv00800 figure 21. expanded register file architecture 7 6543210 working register group pointer expanded register bank/group pointer ff fo 7f 0f 00 z8 register file (bank0) ** register pointer ff fe fd fc fb fa f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 spl sph rp flags imr irq ipr p01m p3m p2m u u 0 u 0 0 u 0 0 1 (f) 0f (f) 0e (f) 0d (f) 0c (f) 0b reserved (f) 01 (f) 00 wdtmr smr u u 0 u u 0 u 1 0 1 u u 0 u u 0 u 0 0 1 u u 0 u u 0 u 0 0 1 u u 0 u u 0 u 1 0 1 u u 0 u u 0 u 1 0 1 u u 0 u u 0 u 0 0 1 u u 0 u u 0 u 1 0 1 uu u 0 1 101 001000u0 register** expanded reg. bank/group (f) reset condition register** z8 ? standard control registers reset condition d7 d6 d5 d4 d3 d2 d1 d0 reserved * * * ? reserved smr2 reserved reserved uuuuu uu u uu u uuu u u uu u uu u uu uu u u u uu u 0 0 000000 0u u 00 00 0 reserved pcon u 0 * 00 0 0uu uu uu uuuuuu uu uu uu u u u u u uu u uu register** expanded reg. group (0) reset condition (0) 03 p3 (0) 02 p2 (0) 01 p1 (0) 00 p0 u = unknown * will not be reset with a stop-mode recovery ** all addresses are in hexadecimal * * ? will not be reset with a stop-mode recovery, except bit 0. reserved reserved reserved reserved reserved u 0 u0 0 0uu expanded reg. bank/group (d) register** (d) 0c (d) 0b (d) 0a (d) 09 (d) 08 (d) 07 (d) 06 (d) 05 (d) 04 (d) 03 (d) 02 reserved hi8 l08 hi16 l016 tc16h tc16l tc8h tc8l reserved ctr2 reset condition u uu u uuuuuuu u u u u u u u 0 uuuuu u u u u u u u uuuuuu u u u u u u u u u u u u uuu0 uuuu u u u u uu uuu uuu uuu (d) 01 ctr1 (d) 00 ctr0 0 0 uuuuu u 0 uuuuuu reserved u u u u u u 0 reserved reserved reserved reserved reserved reserved reserved reserved (f) 0a (f) 09 (f) 08 (f) 07 (f) 06 (f) 05 (f) 04 (f) 03 (f) 02
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 29 1 register file . the register file (bank 0) consists of four i/o port registers, 236 general-purpose registers, and 16 con- trol and status registers (r0-r3, r4-r239, and r240- r255, respectively), plus two expanded registers groups (banks d and f). instructions can access registers directly or indirectly through an 8-bit address field. this allows a short, 4-bit register address using the register pointer (figure 23). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 contin- uous locations. the register pointer addresses the start- ing location of the active working register group. note: working register group e0-ef can only be access- ed through working registers and indirect addressing modes. stack. the z86lxx external data memory or the internal register file is used for the stack. an 8-bit stack pointer (r255) is used for the internal stack that resides in the gen- eral-purpose registers (r4-r239). sph is used as a gen- eral-purpose register only when using internal stacks. note: when sph is used as a general-purpose register and port 0 is in address mode, the contents of sph will be loaded into port 0 whenever the internal stack is accessed. counter/timer register description register description hi8(d)%0b: holds the captured data from the output of the 8-bit counter/timer0. this register is typically used to hold the number of counts when the input signal is 1. l08(d)%0a: holds the captured data from the output of the 8-bit counter/timer0. this register is typically used to hold the number of counts when the input signal is 0. figure 22. register pointer register d7 d6 d5 d4 d3 d2 d1 d0 expanded register file pointer working register pointer r253 rp default setting after reset = 0000 0000 figure 23. register pointer the upper nibble of the register file address provided by the register pointer specifies the active working-register group r 7 r 6 r 5 r 4 r253 i/o ports specified working register group the lower nibble of the register file address provided by the instruction points to the specified register r 3 r 2 r 1 r 0 register group 0 7f register group 1 6f 5f 4f 3f 2f 1f 0f 00 10 20 30 40 50 60 70 r15 to r0 r15 to r4 * r3 to r0 * table 4. expanded register group d (d)%0c reserved (d)%0b hi8 (d)%0a lo8 (d)%09 hi16 (d)%08 lo16 (d)%07 tc16h (d)%06 tc16l (d)%05 tc8h (d)%04 tc8l (d)%03 reserved (d)%02 ctr2 (d)%01 ctr1 (d)%00 ctr0 field bit position description t8_capture_hi 76543210 r w captured data no effect field bit position description t8_capture_l0 76543210 r w captured data no effect
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 30 p r e l i m i n a r y ds96lv00800 hi16(d)%09: holds the captured data from the output of the 16-bit counter/timer16. this register holds the ms- byte of the data. l016(d)%08: holds the captured data from the output of the 16-bit counter/timer16. this register holds the ls- byte of the data. tc16h(d)%07: counter/timer2 ms-byte hold register. tc16l(d)%06: counter/timer2 ls-byte hold register. tc8h(d)%05: counter/timer8 high hold register. tc8l(d)%04: counter/timer8 low hold register. field bit position description t16_capture_hi 76543210 r w captured data no effect field bit position description t16_capture_l o 76543210 r w captured data no effect field bit position description t16_data_hi 76543210 r/w data field bit position description t16_data_lo76543210 r/w data field bit position description t8_level_hi 76543210 r/w data field bit position description t8_level_lo 76543210 r/w data
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 31 1 ctr0 (d)00: counter/timer8 control register. ctr0: counter/timer8 control register description t8 enable. this field enables t8 when set (written) to 1. single/modulo-n. when set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. when set to 1 (single pass), the counter stops when the terminal count is reached. time-out. this bit is set when t8 times out (terminal count reached). to reset this bit, a 1 should be written to this lo- cation. this is the only way to reset this status condi- tion, therefore, care should be taken to reset this bit prior to using/enabling the counter/timers . note: care must be taken when utilizing the or or and commands to manipulate ctr0, bit 5 and ctr1, bits 0 and 1 (demodulation mode). these instructions use a read-modify-write sequence in which the current status from the ctr0 and ctr1 registers will be ored or anded with the designated value and then written back into the registers. example: when the status of bit 5 is 1, a timer reset condition will occur. t8 clock. defines the frequency of the input signal to t8. capture_int_mask. set this bit to allow interrupt when data is captured into either lo8 or hi8 upon a positive or negative edge detection in demodulation mode. counter_int_mask. set this bit to allow interrupt when t8 has a time out. p34_out. this bit defines whether p34 is used as a normal output pin or the t8 output. field bit position value description t8_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------- r/w 0 1 modulo-n single pass time_out --5------ r w 0 1 0 1 no counter time-out counter time-out occurred no effect reset flag to 0 t8 _clock ---43--- r/w 0 0 0 1 1 0 1 1 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0 1 disable data capture int. enable data capture int. counter_int_mask ------1- r/w 0 1 disable time-out int. enable time-out int. p34_out -------0 r/w 0* 1 p34 as port output t8 output on p34 note: * indicates the value upon power-on reset.
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 32 p r e l i m i n a r y ds96lv00800 ctr1(d)%01: controls the functions in common with the t8 and t16. field bit position value description mode 7------- r/w 0* transmit mode demodulation mode p36_out/demodulator _input -6------ r/w 0* 1 0 1 transmit mode port output t8/t16 output demodulation mode p31 p20 t8/t16_logic/ edge _detect --54---- r/w 00 01 10 11 00 01 10 11 transmit mode and or nor nand demodulation mode falling edge rising edge both edges reserved transmit_submode/ glitch_filter ----32-- r/w 00 01 10 11 00 01 10 11 transmit mode normal operation ping-pong mode t16_out = 0 t16_out = 1 demodulation mode no filter 4 sclk cycle 8 sclk cycle 16 sclk cycle initial_t8_out/ rising edge ------1- r/w r w 0 1 0 1 0 1 transmit mode t8_out is 0 initially t8_out is 1 initially demodulation mode no rising edge rising edge detected no effect reset flag to 0 initial_t16_out/ falling_edge -------0 r/w r w 0 1 0 1 0 1 transmit mode t16_out is 0 initially t16_out is 1 initially demodulation mode no falling edge falling edge detected no effect reset flag to 0 note: *default upon power-on reset
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 33 1 ctr1 register description mode. if it is 0, the counter/timers are in the transmit mode, otherwise they are in the demodulation mode. p36_out/demodulator_input. in transmit mode, this bit defines whether p36 is used as a normal output pin or the combined output of t8 and t16. in demodulation mode, this bit defines whether the input signal to the counter/timers is from p20 or p31. t8/t16_logic/edge _detect. in transmit mode, this field defines how the outputs of t8 and t16 are combined (and, or, nor, nand). in demodulation mode, this field defines which edge should be detected by the edge detector. transmit_submode/glitch filter . in transmit mode, this field defines whether t8 and t16 are in the "ping-pong" mode or in independent normal operation mode. setting this field to "normal operation mode" terminates the "ping- pong mode" operation. when set to 10, t16 is immediate- ly forced to a 0; a setting of 11 will force t16 to output a 1. in demodulation mode, this field defines the width of the glitch that should be filtered out. initial_t8_out/rising_edge. in transmit mode, if 0, the output of t8 is set to 0 when it starts to count. if 1, the out- put of t8 is set to 1 when it starts to count. when the counter is not enabled and this bit is set to 1 or 0, t8_out will be set to the opposite state of this bit. this insures that when the clock is enabled a transition occurs to the initial state set by ctr1, d1. in demodulation mode, this bit is set to 1 when a rising edge is detected in the input signal. in order to reset it, a 1 should be written to this location. initial_t16 out/falling _edge . in transmit mode, if it is 0, the output of t16 is set to 0 when it starts to count. if it is 1, the output of t16 is set to 1 when it starts to count. this bit is effective only in normal or ping-pong mode (ctr1, d3, d2). when the counter is not enabled and this bit is set, t16_out will be set to the opposite state of this bit. this insures that when the clock is enabled a transition oc- curs to the initial state set by ctr1, d0. in demodulation mode, this bit is set to 1 when a falling edge is detected in the input signal. in order to reset it, a 1 should be written to this location. note: modifying ctr1, (d1 or d0) while the counters are enabled will cause un-predictable output from t8/16_out.
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 34 p r e l i m i n a r y ds96lv00800 ctr2 (d)%02: counter/timer16 control register. ctr2 description t16_enable . this field enables t16 when set to 1. single/modulo-n. in transmit mode, when set to 0, the counter reloads the initial value when terminal count is reached. when set to 1, the counter stops when the termi- nal count is reached. in demodulation mode, when set to 0 , t16 captures and reloads on detection of all the edges; when set to 1, t16 captures and detects on the first edge, but ignores the sub- sequent edges. for details, see the description of t16 de- modulation mode. time_out. this bit is set when t16 times out (terminal count reached). in order to reset it, a 1 should be written to this location. t16_clock. defines the frequency of the input signal to counter/timer16. capture_int_mask. set this bit to allow interrupt when data is captured into lo16 and hi16. counter_int_mask. set this bit to allow interrupt when t16 times out. p35_out. this bit defines whether p35 is used as a normal output pin or t16 output. field bit position value description t16_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------ r/w 0 1 0 1 transmit mode modulo-n single pass demodulation mode t16 recognizes edge t16 does not recognize edge time_out --5----- r w 0 1 0 1 no counter time-out counter time-out occurred no effect reset flag to 0 t16 _clock ---43--- r/w 00 01 10 11 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0 1 disable data capture int. enable data capture int. counter_int_mask ------1- r/w 0 disable time-out int. enable time-out int. p35_out -------0 r/w 0* 1 p35 as port output t16 output on p35 note: * indicates the value upon power-on reset.
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 35 1 smr2(f)%0d: stop-mode recovery register 2. field bit position value description reserved 7------- 0 reserved (must be 0) recovery level -6------ w0* 1 low high reserved --5----- 0 reserved (must be 0) source ---432-- w 000* 001 010 011 100 101 110 111 a. por only b. nand of p23-p20 c. nand or p27-p20 d. nor of p33-p31 e. nand of p33-p31 f. nor of p33-p31, p00,p07 g. nand of p33-p31,p00,p07 h. nand of p33-p31,p22-p20 reserved ------10 00 reserved (must be 0) notes: * indicates the value upon power-on reset port pins configured as outputs are ignored as a smr recovery source.
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 36 p r e l i m i n a r y ds96lv00800 counter/timer functional blocks figure 24. glitch filter circuitry glitch filter edge detector ctr1 d5,d4 ctr1 d3,d2 pos edge neg edge mux ctr1 d6 p31 p20 figure 25. 8-bit counter/timer circuits z8 data bus pos edge neg edge ctr0 d2 irq4 ctr0 d1 t8_out tc8l tc8h clock select sclk ctr0 d4, d3 clock 8-bit counter t8 hi8 lo8 z8 data bus
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 37 1 input circuit the edge detector monitors the input signal on p31 or p20. based on ctr1 d5-d4, a pulse is generated at the pos edge or neg edge line when an edge is detected. glitches in the input signal which have a width less than specified (ctr1 d3, d2) are filtered out. t8 transmit mode before t8 is enabled, the output of t8 depends on ctr1, d1. if it is 0, t8_out is 1. if it is 1, t8_out is 0. when t8 is enabled, the output t8_out switches to the initial value (ctr1 d1). if the initial value (ctr1 d1) is 0, tc8l is loaded, otherwise tc8h is loaded into the counter. in single-pass mode (ctr0 d6), t8 counts down to 0 and stops, t8_out toggles, the time-out status bit (ctr0 d5) is set, and a time-out interrupt can be generat- ed if it is enabled (ctr0 d1) (figure 26). in modulo-n mode, upon reaching terminal count, t8_out is toggled, but no interrupt is generated. then t8 loads a new count (if the t8_out level now is 0), tc8l is loaded; if it is 1, tc8h is loaded. t8 counts down to 0, toggles t8_out, sets the time-out status bit (ctr0 d5) and generates an interrupt if enabled (ctr0 d1) (figure 27). this completes one cycle. t8 then loads from tc8h or tc8l according to the t8_out level, and repeats the cycle. the user can modify the values in tc8h or tc8l at any time. the new values take effect when they are loaded. care must be taken not to write these registers at the time the values are to be loaded into the counter/timer, to en- sure known operation. an initial count of 1 is not al- lowed (a non-function will occur). an initial count of 0 will cause tc8 to count from 0 to %ff to %fe (note, % is used for hexadecimal values). transition from 0 to %ff is not a time-out condition. note: using the same instructions for stopping the counter/timers and setting the status bits is not rec- ommended. two successive commands, first stopping the counter/timers, then resetting the status bits is neces- sary. this is required because it takes one counter/timer clock interval for the initiated event to actually occur. figure 26. t8_out in single-pass mode tc8h counts counter enable command, t8_out switches to its initial value (ctr1 d1) t8_out toggles, time-out interrupt figure 27. t8_out in modulo-n mode counter enable command, t8_out switches to its initial value (ctr1 d1) t8_out toggles t8_out tc8l tc8h tc8l tc8h tc8l time-out interrupt time-out interrupt
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 38 p r e l i m i n a r y ds96lv00800 t8 demodulation mode the user should program tc8l and tc8h to %ff. after t8 is enabled, when the first edge (rising, falling, or both depending on ctr1 d5, d4) is detected, it starts to count down. when a subsequent edge (rising, falling, or both de- pending on ctr1 d5, d4) is detected during counting, the current value of t8 is one's complemented and put into one of the capture registers. if it is a positive edge, data is put into lo8, if negative edge, hi8. one of the edge detect status bits (ctr1 d1, d0) is set, and an interrupt can be generated if enabled (ctr0 d2). meanwhile, t8 is loaded with %ff and starts counting again. should t8 reach 0, the time-out status bit (ctr0 d5) is set, an interrupt can be generated if enabled (ctr0 d1), and t8 continues count- ing from %ff (figure 28). figure 28. demodulation mode count capture flowchart t8 (8-bit) count capture t8_enable (set by user) no yes edge present no yes what kind of edge pos t8 ? l08 neg t8 ? hi8 %ff ? t8
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 39 1 figure 29. transmit mode flowchart t8 (8-bit) transmit mode t8_enable bit set ctr0, d7 no yes ctr1, d1 value 1 load tc8l reset t8_out load tc8h set t8_out enable t8 reset t8_enable bit set time-out status bit (ctr0 d5) and generate timeout_int if enabled no t8_timeout yes single pass? modulo-n t8_out value load tc8l reset t8_out load tc8h set t8_out enable t8 no t8_timeout disable t8 yes set time-out status bit (ctr0 d5) and generate timeout_int if enabled single pass 0 1 0
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 40 p r e l i m i n a r y ds96lv00800 figure 30. demodulation mode flowchart t8 (8-bit) demodulation mode t8_enable ctr0, d7 no yes first edge present no t8_enable bit set yes set edge present status bit and trigger data capture int. if enabled no %ff ? tc8 yes enable tc8 edge present disable t8 yes t8 time out yes set time-out status bit and trigger time out int. if enabled no continue counting
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 41 1 t16 transmit mode in normal or ping-pong mode, the output of t16 when not enabled is dependent on ctr1, d0. if it is a 0, t16_out is a 1; if it is a 1, t16_out is 0. the user can force the out- put of t16 to either a 0 or 1 whether it is enabled or not by programming ctr1 d3, d2 to a 10 or 11. when t16 is enabled, tc16h * 256 + tc16l is loaded, and t16_out is switched to its initial value (ctr1 d0). when t16 counts down to 0, t16_out is toggled (in nor- mal or ping-pong mode), an interrupt is generated if en- abled (ctr2 d1), and a status bit (ctr2 d5) is set. note that global interrupts will override this function as de- scribed in the interrupts section. if t16 is in single-pass mode, it is stopped at this point. if it is in modulo-n mode, it is loaded with tc16h * 256 + tc16l and the counting continues. the user can modify the values in tc16h and tc16l at any time. the new values take effect when they are load- ed. care must be taken not to load these registers at the time the values are to be loaded into the counter/timer, to ensure known operation. an initial count of 1 is not al- lowed. an initial count of 0 will cause t16 to count from 0 to %ff ff to %fffe. transition from 0 to %ffff is not a time-out condition. figure 31. 16-bit counter/timer circuits z8 data bus pos edge neg edge ctr2 d2 irq3 ctr2 d1 t16_out tc16l tc16h clock select sclk ctr2 d4, d3 clock 16-bit counter t16 hi16 lo16 z8 data bus
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 42 p r e l i m i n a r y ds96lv00800 t16 demodulation mode the user should program tc16l and tc16h to %ff. after t16 is enabled, when the first edge (rising, falling, or both depending on ctr1 d5, d4) is detected, t16 captures hi16 and lo16, reloads and begins counting. if d6 of ctr2 is 0: when a subsequent edge (rising, fall- ing, or both depending on ctr1 d5, d4) is detected during counting, the current count in t16 is one's complemented and put into hi16 and lo16. when data is captured, one of the edge detect status bits (ctr1 d1, d0) is set and an interrupt is generated if enabled (ctr2 d2). t16 is loaded with %ffff and starts again. this t16 mode is generally used to measure space time; the length of time between bursts of carrier signal(marks). if d6 of ctr2 is 1: t16 ignores the subsequent edges in the input signal and continues counting down. a time out of t8 will cause t16 to capture its current value and gen- erate an interrupt if enabled (ctr2, d2). in this case, t16 does not reload and continues counting. if d6 bit of ctr2 is toggled (by writing a 0 then a 1 to it), t16 will capture and reload on the next edge (rising, falling, or both depending on ctr1 d5, d4) but continue to ignore subsequent edg- es. this t16 mode is generally used to measure mark times; the length of an active carrier signal bursts. should t16 reach 0, it continues counting from %ffff; meanwhile, a status bit (ctr2 d5) is set and an interrupt time-out can be generated if enabled (ctr2 d1). figure 32. t16_out in single-pass mode tc16h*256+tc16l counts counter enable command, t16_out switches to its initial value (ctr1 d0) t16_out toggles, time-out interrupt figure 33. t16_out in modulo-n mode tc16h*256+tc16l counter enable command, t16_out switches to its initial value (ctr1 d0) t16_out toggles, time-out interrupt tc16h*256+tc16l tc16h*256+tc16l t16_out toggles, time-out interrupt t16_out
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 43 1 ping-pong mode this operation mode is only valid in transmit mode. t8 and t16 need to be programmed in single-pass mode (ctr0 d6, ctr2 d6) and ping-pong mode needs to be programmed in ctr1 d3, d2. the user can begin the op- eration by enabling either t8 or t16 (ctr0 d7 or ctr2 d7). for example, if t8 is enabled, t8_out is set to this initial value (ctr1 d1). according to t8_out's level, tc8h or tc8l is loaded into t8. after the terminal count is reached, t8 is disabled and t16 is enabled. t16_out switches to its initial value (ctr1 d0), data from tc16h and tc16l is loaded, and t16 starts to count. after t16 reaches the terminal count it stops, t8 is enabled again, and the whole cycle repeats. interrupts can be allowed when t8 or t16 reaches terminal control (ctr0 d1, ctr2 d1). to stop the ping-pong operation, write 00 to bits d3 and d2 of ctr1. note: enabling ping-pong operation while the counter/timers are running may cause intermittent counter/timer function. disable the counter/timers, then reset the status flags prior to instituting this operation. to initiate ping-pong mode first, make sure both counter/timers are not running. then set t8 into single-pass mode (ctr0 d6), set t16 into sin- gle-pass mode (ctr2 d6), and set ping-pong mode (ctr1 d2, d3). these instructions do not have to be in any particular order. finally, start ping-pong mode by en- abling either t8 (ctr0 d7) or t16 (ctr2 d7). during ping-pong mode the enable bits of t8 and t16 (ctr0 d7, ctr2 d7) will be set and cleared alternately by hardware. the time-out bits (ctr0 d5, ctr2 d5) will be set every time the counter/timers reach the terminal count. figure 34. ping-pong mode enable tc8 time-out enable tc16 time-out ping-pong ctr1 d3,d2
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 44 p r e l i m i n a r y ds96lv00800 figure 35. output circuit and/or/nor/nand logic t8_out ctr1 d5,d4 p34_internal ctr0 d0 p36_internal ctr1 d6 p35_internal ctr2 d0 p35_ext p36_ext p34_ext mux mux mux t16_out mux ctr1, d2 ctr1 d3
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 45 1 interrupts . the z86lxx has five different interrupts. the interrupts are maskable and prioritized (figure 36). the five sources are divided as follows: three sources are claimed by port 3 lines p33-p31, the remaining two by the counter/timers (table 5). the interrupt mask register glo- bally or individually enables or disables the five interrupt requests. figure 36. interrupt block diagram interrupt edge select irq register (d6, d7) irq 1, 3, 4 irq imr ipr priority logic 5 vector select irq0 irq2 global interrupt enable interrupt request
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 46 p r e l i m i n a r y ds96lv00800 when more than one interrupt is pending, priorities are re- solved by a programmable priority encoder controlled by the interrupt priority register. an interrupt machine cycle is activated when an interrupt request is granted. this dis- ables all subsequent interrupts, saves the program counter and status flags, and then branches to the pro- gram memory vector location reserved for that interrupt. all z86lxx interrupts are vectored through locations in the program memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. an interrupt resulting from an1 is mapped into irq2, and an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 may be rising, falling, or both edge trig- gered, and are programmable by the user. the software can poll to identify the state of the pin. programming bits for the interrupt edge select are located in the irq register (r250), bits d7 and d6 . the configu- ration is shown in table 6. clock. the z86lxx on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, lc, ceramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal should be at cut, 1 mhz to 8 mhz maximum, with a series resistance (rs) less than or equal to 100 ohms. the z86lxx on-chip oscillator may be driven with a low cost rc network or oth- er suitable external clock source. for 32 khz crystal operation, an external feedback resistor (rf) and a serial resistor (rd) are required. see figure 37. the crystal should be connected across xtal1 and xtal2 using the recommended capacitors (capacitance greater than or equal to 22 pf) from each pin to ground. the rc oscillator configuration is an external resistor con- nected from xtal1 to xtal2, with a frequency-setting ca- pacitor from xtal1 to ground (figure 37). table 5. interrupt types, sources, and vectors name source vector location comments irq0 /dav0, irq0 0, 1 external (p32), rising falling edge triggered irq1, irq1 2, 3 external (p33), falling edge triggered irq2 /dav2, irq2, tin 4, 5 external (p31), rising falling edge triggered irq3 t16 6, 7 internal irq4 t8 8, 9 internal table 6. irq register irq interrupt edge d7 d6 irq2(p31) irq0 (p32) 00 f f 01 f r 10 r f 1 1 r/f r/f notes: f = falling edge r = rising edge in analog mode, the stop-mode recovery sources selected by the smr register are connected to the irq1 input. any of the stop-mode recovery sources for smr (except p31, p32, and p33) can be used to generate irq1 (falling edge triggered).
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 47 1 power-on reset (por). a timer circuit clocked by a ded- icated on-board rc oscillator is used for the power-on re- set (por) timer function. the por time allows v cc and the oscillator circuit to stabilize before instruction execu- tion begins. the por timer circuit is a one-shot timer triggered by one of three conditions: 1. power fail to power ok status including waking up from (v lv standby). 2. stop-mode recovery (if d5 of smr = 1). 3. wdt time-out. the por time is a nominal 5 ms. bit 5 of the stop-mode register determines whether the por timer is bypassed after stop-mode recovery (typical for external clock, rc, lc oscillators). halt. halt turns off the internal cpu clock, but not the xtal oscillation. the counter/timers and external inter- rupts irq0, irq1, irq2, irq3, and irq4 remain active. the devices are recovered by interrupts, either externally or internally generated. an interrupt request must be exe- cuted (enabled) to exit halt mode. after the interrupt ser- vice routine, the program continues from the instruction af- ter the halt. stop. this instruction turns off the internal clock and ex- ternal crystal oscillation and reduces the standby current to 10 m a or less. stop mode is terminated only by a reset, such as wdt time-out, por, smr, or external reset. this causes the processor to restart the application program at address 000ch. in order to enter stop (or halt) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. to do this, the user must execute a nop (opcode = ffh) immediately be- fore the appropriate sleep instruction, i.e., ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode figure 37. oscillator con?uration xtal1 xtal2 c1 c2 c1 c2 c1 xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal c1, c2 = 47 pf typ * f = 8 mhz lc c1, c2 = 22 pf l = 130 m h * f = 3 mhz * rc @ 3v vcc (typ) c1 = 33 pf * r = 1k * external clock l r * preliminary value including pin parasitics c1 32 khz xtal c1 = 20 pf, c = 33 pf rd = 56 - 470k rf =10 m rf c2 rd xtal1 xtal2
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 48 p r e l i m i n a r y ds96lv00800 port configuration register (pcon). the pcon regis- ter configures the comparator output on port 3. it is locat- ed in the expanded register file at bank f, location 00 (fig- ure 38). comparator output port 3 (d0). bit 0 controls the comparator used in port 3. a 1 in this location brings the comparator outputs to p34 and p37, and a 0 releases the port to its standard i/o configuration. stop-mode recovery register (smr). this register se- lects the clock divide value and determines the mode of stop-mode recovery (figure 39). all bits are write only ex- cept bit 7, which is read only. bit 7 is a flag bit that is hard- ware set on the condition of stop recovery and reset by a power-on cycle. bit 6 controls whether a low level or a high level is required from the recovery source. bit 5 con- trols the reset delay after recovery. bits d2, d3, and d4, or the smr register, specify the source of the stop-mode re- covery signal. bits d0 determines determines if sclk/tclk are divided by 16 or not. the smr is located in bank f of the expanded register group at address 0bh. figure 38. port con?uration register (pcon) (write only) reserved (must be 1) d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h comparator output port 3 0 p34, p37 standard output* 1 p34, p37 comparator output * default setting after reset figure 39. stop-mode recovery register figure 40. sclk circuit d7 d6 d5 d4 d3 d2 d1 d0 smr (f) 0b sclk/tclk divide-by-16 0 off 1 on reserved (must be 0) stop-mode recovery source 000 001 010 011 100 101 11 0 111 stop delay 0 off 1 on stop recovery level 0 low 1 high stop flag 0 por 1 stop recovery * default setting after reset ** default setting after reset and stop-mode recovery ** * * * * por only reserved p31 p32 p33 p27 p2 nor 0-3 p2 nor 0-7 smr, d0 ? 2 ? 16 osc sclk tclk
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 49 1 figure 41. stop-mode recovery source p00 p32 vcc p31 p32 p33 p27 p20 p23 p20 p27 smr d4 0 d3 0 d2 0 smr d4 0 d3 1 d2 0 smr d4 0 d3 1 d2 1 smr d4 1 d3 0 d2 0 smr d4 1 d3 0 d2 1 smr d4 1 d3 1 d2 0 smr d4 1 d3 1 d2 1 smr2 d4 0 d3 0 d2 0 smr2 d4 0 d3 1 d2 0 smr2 d4 0 d3 1 d2 1 smr2 d4 1 d3 0 d2 0 smr2 d4 1 d3 0 d2 1 smr2 d4 1 d3 1 d2 0 smr2 d4 1 d3 1 d2 1 smr2 d4 0 d3 0 d2 1 vcc p20 p32 p23 p20 p27 p31 p33 p31 p33 p32 p31 p33 p00 p07 p32 p31 p33 p07 p20 p32 p31 p33 p21 p22 smr2 d6 smr d6 to reset and wdt circuitry (active low) s1 s2 s3 s4 to irq1
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 50 p r e l i m i n a r y ds96lv00800 sclk/tclk divide-by-16 select (d0). d0 of the smr controls a divide-by-16 prescaler of sclk/tclk. the pur- pose of this control is to selectively reduce device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources interrupt logic). after stop-mode recovery, this bit is set to a 0. stop-mode recovery source (d2, d3, and d4). these three bits of the smr specify the wake up source of the stop recovery (figure 41 and table 7). note: any port 2 bit defined as an output will drive the cor- responding input to the default state to allow the remaining inputs to control the and/or function. refer to smr2 reg- ister for other recover sources. stop-mode recovery delay select (d5). this bit, if low, disables the 5 ms /reset delay after stop-mode recov- ery. the default configuration of this bit is one. if the "fast" wake up is selected, the stop-mode recovery source needs to be kept active for at least 5tpc. stop-mode recovery edge select (d6). a 1 in this bit po- sition indicates that a high level on any one of the recovery sources wakes the z86lxx from stop mode. a 0 indi- cates low level recovery. the default is 0 on por (figure 36). cold or warm start (d7). this bit is set by the device upon entering stop mode. it is a read only flag bit. a 1 in d7 (warm) indicates that the device will awaken from a smr source or a wdt while in stop mode. a 0 in this bit (cold) indicates that the device will be reset by a por, wdt while not in stop, or the device awakened from a low voltage standby mode. stop-mode recovery register 2 (smr2). this register determines the mode of stop-mode recovery for smr2 figure 42). if smr2 is used in conjunction with smr, either of the specified events will cause a stop-mode recovery. note: port pins configured as outputs are ignored as a smr or smr2 recovery source. for example, if the nand or p23-p20 is selected as the recovery source and p20 is configured as an output then the remaining smr pins (p23-p21) form the nand equation. table 7. stop-mode recovery source smr:432 operation description of action d4 d3 d2 description of action 0 0 0 por and/or external reset recovery 0 0 1 reserved 0 1 0 p31 transition 0 1 1 p32 transition 1 0 0 p33 transition 1 0 1 p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 51 1 figure 42. stop-mode recovery register 2 ((0f) dh: d2-d4, d6 write only) d7 d6 d5 d4 d3 d2 d1 d0 smr2 (0f) dh reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 por only* 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p23, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level 0 low* 1 high reserved (must be 0) note: if used in conjunction with smr, either of the two specified events will cause a stop-mode recovery. *default setting after reset
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 52 p r e l i m i n a r y ds96lv00800 watch-dog timer mode register (wdtmr). the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt must initially be en- abled by executing the wdt instruction and refreshed on subsequent executions of the wdt instruction. the wdt circuit is driven by an on-board rc oscillator or external oscillator from the xtal1 pin. the wdt instruction affects the zero (z), sign (s), and overflow (v) flags. the por clock source is selected with bit 4 of the wdt register. bit 0 and 1 control a tap circuit that determines the time-out period. bit 2 determines whether the wdt is ac- tive during halt and bit 3 determines wdt activity during stop. bits 5 through 7 are reserved (figure 42). this reg- ister is accessible only during the first 61 processor cycles (122 xtal clocks) from the execution of the first instruc- tion after power-on-reset, watch-dog reset, or a stop- mode recovery (figure 43). after this point, the register cannot be modified by any means, intentional or other- wise. the wdtmr cannot be read and is located in bank f of the expanded register group at address location 0fh. it is organized as follows: figure 43. watch-dog timer mode register (write only) d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (0f) 0f wdt tap int rc osc external clock 00 5 ms 256 tpc 01 10 ms 512 tpc 10 20 ms 1024 tpc 11 80 ms 4096 tpc wdt during halt 0 off 1 on wdt during stop 0 off 1 on xtal1/int rc select for wdt 0 on-board rc 1 xtal reserved (must be 0) * default setting after reset * * * *
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 53 1 wdt time select (d0, d1). selects the wdt time period. it is configured as shown in table 8. wdtmr during halt (d2). this bit determines whether or not the wdt is active during halt mode. a 1 indicates active during halt. the default is 1. wdtmr during stop (d3). this bit determines whether or not the wdt is active during stop mode. since the xtal clock is stopped during stop mode, the on-board rc has to be selected as the clock source to the wdt/por counter. a 1 indicates active during stop. the default is 1. clock source for wdt (d4). this bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1, the internal rc oscil- lator is bypassed and the por and wdt clock source is driven from the external pin, xtal1. the default configu- ration of this bit is 0, which selects the rc oscillator. table 8. wdt time select d1 d0 time-out of internal rc osc time-out of xtal clock 0 0 5 ms min 256 tpc 0 1 10 ms min 512 tpc 1 0 20 ms min 1024 tpc 1 1 80 ms min 4096 tpc notes: tpc = xtal clock cycle. the default on reset is 10 ms. figure 44. resets and wdt clk 18 clock reset generator reset * /clr 2 wdt tap select internal rc osc. clk *clr1 por wdt1 234 low operating voltage det. internal reset active high ck source select (wdtmr) xtal vdd vbo/vlv 2v ref. from stop mode recovery source wdt stop delay select (smr) 12 ns glitch filter + - 5 clock filter wdt/por counter chain m u x /reset * /clr1 and /clr2 enable the wdt/por and 18 clock reset timers upon a low to high input translation. vcc
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 54 p r e l i m i n a r y ds96lv00800 mask selectable options . there are seven mask select- able options to choose from based on rom code require- ments. these are: low voltage detection/standby . an on-chip voltage comparator checks that the v cc is at the required level for correct operation of the device. reset is globally driven when v cc falls below v lv (vrf1). a small further drop in v cc causes the xtal1 and xtal2 circuitry to stop the crystal or resonator clock. typical low-voltage power con- sumpion in this low voltage standby mode (i lv ) is about 45 m a (varying with the number of mask selectable options enabled). if the v cc is allowed to stay above vram, the ram content is preserved. when the power level is re- turned to above v lv , the device will perform a por and function normally (figure 45). the minimum operating voltage varies with the tempera- ture and operating frequency, while v lv varies with tem- perature only. the low voltage trip voltage (v lv ) is less than 2.1v under the following conditions: maximum (v lv ) conditions: t a = 0 c, +55 c internal clock frequency equal to or less than 4.0 mhz note: the internal clock frequency is one-half the external clock frequency. ram protect on/off rc/other rc/xtal 32 khz xtal on/off port 04-07 pull-ups on/off port 00-03 pull-ups on/off port 20-27 pull-ups on/of port 30-33 pull-ups on/of port 3 mouse mode 0.4 v dd tr i p on/off figure 45. typical z86lxx low voltage vs temperature at 8 mhz 0 15 25 35 45 55 1.8 1.6 1.4 1.2 1 1.8 0.6 0.4 0.2 0 vlv vlv temperature
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 55 1 expanded register file control registers (0d) figure 46. tc8 control register ((0d) oh: read/write except where noted) d7 d6 d5 d4 d3 d2 d1 d0 ctr0 (0d) 0h 0 p34 as port output* 1 timer8 output 0 disable t8 time out interrupt 1 enable t8 time out interrupt 0 disable t8 data capture interrupt 1 enable t8 data capture interrupt 00 sclk on t8 01 sclk/2 on t8 10 sclk/4 on t8 11 sclk/8 on t8 r 0 no t8 counter time out r 1 t8 counter time out occured w 0 no effect w 1 reset flag to 0 * default setting after reset 0 modulo-n 1 single pass r 0 t8 disabled * r 1 t8 enabled w 0 stop t8 w 1 enable t8
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 56 p r e l i m i n a r y ds96lv00800 d7 d6 d5 d4 d3 d2 d1 d0 ctr1 (0d) 1h 0 t16_out is 0 initially 1 t16_out is 1 initially r/w r r w w 0 no falling edge detection 1 falling edge detection 0 no effect 1 reset flag to 0 0 t8_out is 0 initially 1 t8_out is 1 initially 0 no rising edge detection 1 rising edge detection 0 0 normal operation 0 1 ping-pong mode 1 0 t16_out = 0 1 1 t16_out = 1 transmit mode/t8/t16 logic 0 0 falling edge detection 0 1 rising edge detection 1 0 both edge detection 1 1 reserved 0 p36 as port output * 1 p36 as t8/t16_out 0 transmit mode * 1 demodulation mode 0 0 no filter 0 1 4 sclk cycle filter 1 0 8 sclk cycle filter 1 1 16 sclk cycle filter demodulation mode transmit mode transmit mode r/w demodulation mode r r w w transmit mode demodulation mode 0 0 and 0 1 or 1 0 nor 1 1 nand demodulation mode transmit mode 0 p31 as demodulator input 1 p20 as demodulator input demodulation mode transmit/demodulation modes 0 no effect 1 reset flag to 0 note: care must be taken in differentiating transmit mode from demodulation mode. depending on which of these two modes is operating, the ctr1 bit will have different functions. note: changing from one mode to another cannot be done without disabling the counter/timers. *default setting after reset
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 57 1 figure 48. t16 control register ((0d) 2h: read/write except where noted) d7 d6 d5 d4 d3 d2 d1 d0 ctr2 (0d) 02h 0 p35 is port output* 1 p35 is tc16 output 0 disable t16 time-out interrupt 1 enable t16 time-out interrupt 0 0 sclk on t16 0 1 sclk/2 on t16 1 0 sclk/4 on t16 1 1 sclk/8 on t16 * default setting after reset 0 disable t16 data capture interrupt 1 enable t16 data capture interrupt r 0 no t16 time out r 1 t16 time out occurs w 0 no effect w 1 reset flag to 0 0 modulo-n for t16 1 single pass for t16 r 0 t16 disabled * r 1 t16 enabled w 0 stop t16 w 1 enable t16 transmit mode 0 t16 recognizes edge 1 t16 does not recognize edge demodulator mode
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 58 p r e l i m i n a r y ds96lv00800 expanded register file control registers (0f) figure 49. stop-mode recovery register ((0f) 0bh: d6-d0 = write only, d7 = read only) d7 d6 d5 d4 d3 d2 d1 d0 smr (0f) 0b sclk/tclk divide-by-16 0 off 1 on reserved (must be 0) stop-mode recovery source 000 001 010 011 100 101 11 0 111 stop delay 0 off 1 on stop recovery level 0 low 1 high stop flag 0 por 1 stop recovery * * * default setting after reset ** default setting after reset and stop-mode recovery ** * * * * por only reserved p31 p32 p33 p27 p2 nor 0-3 p2 nor 0-7
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 59 1 figure 50. stop-mode recovery register 2 ((0f) 0dh: d2-d4, d6 write only) d7 d6 d5 d4 d3 d2 d1 d0 smr2 (0f) 0dh reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 por only* 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p23, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level 0 low* 1 high reserved (must be 0) note: if used in conjunction with smr, either of the two specified events will cause a stop-mode recovery. *default setting after reset
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 60 p r e l i m i n a r y ds96lv00800 figure 51. watch-dog timer register ((0f) 0fh: write only) d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (0f) 0f wdt tap int rc osc external clock 00 5 ms 256 tpc 01 10 ms 512 tpc 10 20 ms 1024 tpc 11 80 ms 4096 tpc wdt during halt 0 off 1 on wdt during stop 0 off 1 on xtal1/int rc select for wdt 0 on-board rc 1 xtal reserved (must be 0) * default setting after reset * * * * figure 52. port con?uration register (pcon) ((0f) 0h: write only) reserved (must be 1) d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h comparator output port 3 0 p34, p37 standard output* 1 p34, p37 comparator output * default setting after reset
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 61 1 z8 standard control register diagrams figure 53. port 2 mode register (f6h: write only) figure 54. port 3 mode register (f7h: write only) d7 d6 d5 d4 d3 d2 d1 d0 p27-p20 i/o definition 0 defines bit as output 1 defines bit as input* r246 p2m *default setting after reset d7 d6 d5 d4 d3 d2 d1 d0 r247 p3m 0 port 2 open drain* 1 port 2 push-pull 0 p32 = input p35 = output 1 p32 = /dav0/rdy0 p35 = rdy0//dav0 0 p31 = input (tin) p36 = output (tout) 1 p31 = /dav2/rdy2 p36 = rdy2//dav2 0 = p31, p32 digital mode 1 = p31, p32 analog mode 00 p33 = input p34 = output 01 p33 = input 10 p34 = /dm p33 = /dav1/rdy1 p34 = rdy1//dav1 11 * default setting after result reserved (must be 0) figure 55. port 0 and 1 mode register (f8h: write only) figure 56. interrupt priority registers ((0) f9h: write only) d7 d6 d5 d4 d3 d2 d1 d0 r248 p01m p00-p03 mode 00 output 01 input* 1x a11-a8 stack selection 0 external 1 internal* p17-p10 mode 00 byte output 01 reserved 10 ad7-ad0 11 high-impedance ad7ad0, /as, /ds, /r//w, a11-a8, a15-a12, if selected p07-p04 mode 00 output 01 input* 1x a15-a12 external memory timing 0 normal* 1 extended * default setting after reset. note: only p00 and p07 are available on z86l71. d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c>a>b 010 a>b>c 011 a>c>b 100 b>c>a 101 c>b>a 110 b>a>c 111 reserved irq1,irq4,priority (group c) 0 irq1>irq4 1 irq4>irq1 irq0,irq2 priority (group b) 0 irq2>irq0 1 irq0>irq2 irq3,irq5priority (group a) 0 irq5>irq3 1 irq3>irq5 reserved (must be 0)
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 62 p r e l i m i n a r y ds96lv00800 figure 57. interrupt request register ((0) fah: read/write) figure 58. interrupt mask register ((0) fbh: read/write) figure 59. flag register ((0) fch: read/write) d7 d6 d5 d4 d3 d2 d1 d0 r250 irq inter edge p31 p32 = 00 p31 p32 - = 01 p31 - p32 = 10 p31 - p32 - = 11 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = t16 irq4 = t8 d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) 1 enables irq4-irq0 (d0 = irq0) 0 master interrupt disable * 1 master interrupt enable r251 imr * default setting after reset reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow tag sign flag zero flag carry flag r252 flags figure 60. register pointer ((0) fdh: read/write) figure 61. stack pointer high ((0) feh: read/write) figure 62. stack pointer low ((0) ffh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 expanded register bank pointer working register pointer r253 rp default setting after reset = 0000 0000 d7 d6 d5 d4 d3 d2 d1 d0 stack pointer upper byte (sp15-sp8) r254 sph d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp7-sp0) r255 spl
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 63 1 package information figure 63. 28-pin dip package diagram figure 64. 28-pin soic package diagram
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 64 p r e l i m i n a r y ds96lv00800 figure 65. 40-pin dip package diagram figure 66. 44-pin plcc package diagram
z86l88/81/86/87/89/73 ir/low-voltage microcontroller ds96lv00800 p r e l i m i n a r y 65 1 figure 67. 44-pin qfp package diagram
z86l88/81/86/87/89/73 ir/low-voltage microcontroller 66 p r e l i m i n a r y ds96lv00800 ordering information z86l88/81/86/87/89/73 8.0 mhz 28-pin dip 40-pin dip z86l8808psc z86l8708psc z86l8108psc z86l8908psc Z86L8608PSC z86l7308psc 28-pin sioc 44-pin plcc 44-pin qfp z86l8808ssc z86l8708vsc z86l8708fsc z86l8108ssc z86l8908vsc z86l8908fsc z86l8608ssc z86l7308vsc z86l7308fsc for fast results, contact your local zilog sales office for as- sistance in ordering the part desired. codes package p = plastic dip f = plastic quad flat pack v = plastic chip carrier s = soic (small outline integrated circuit) temperature s = 0 c to +70 c speed 8 = 8.0 mhz environmental c = plastic standard example: z 86lxx 08 p s c environmental flow temperature package speed product number zilog prefix is a z86lxx, 8 mhz, dip, 0 c to +70 c, plastic standard flow

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